Great needs have arisen in recent years for new technologies which can provide high-density, low-cost interconnections within and between integrated circuits and in other applications within electronic equipment. In response to the emergence of high lead-count LSI and VLSI integrated circuit devices, assembly technologies have been developed which are capable of making connections to up to about 200 input/output pads (I/O's) per chip using wire bonding techniques. However, wire bonding technology cannot cope with the even higher lead-counts which are already available or will soon become available, due, for example, to the problem of finite geometry of wire bonder tips. Other technologies, such as tape-automated bonding (TAB) thus have been receiving much attention for higher through-put and lower cost at high lead count and potential for higher densities.
Additionally, high-density interconnect modules are used for packaging multiple chips in a common package. Such structures contain multiple conductor levels separated by inter-level dielectrics. Vias between the levels provide conductive paths for transmitting signals from one conductor layer to another. The integrated circuits are connected to the high-density multi-layer interconnect modules by wire bonding, TAB, or flip chip area solder bump bonding.
Multi-chip packaging technologies are important, as they overcome a number of the size and performance limitations of single-chip packaging. Multi-chip packaging permits greater chip density and fewer external connections, resulting in improved reliability and delay time. The high interconnect density of multi-chip packaging, however, requires technology that can define high-resolution conductor patterns in multiple layers on relatively large substrates. Fine-line, multi-layer conductor patterns are required to interconnect the large number of I/O's on highly integrated circuits. Interconnections must be short and have well-controlled electrical characteristics, in order to propagate high-speed signals with minimum delay and distortion. Also, thermal considerations can become important, as it is necessary both to remove heat from chips and to match the coefficient of thermal expansion of chips and interconnection structures, to improve reliability of the package. Conventional single-chip packages have limited packing density on printed wiring boards and limit the system speed due to the large delay time for signals to propagate between chips. A number of technologies have been used or proposed for such multi-layer packaging. They are reviewed, for example, in R. J. Jensen, "Polyimides as Interlayer Dielectrics for High-Performance Interconnections of Integrated Circuits," chapter 40 in M. J. Bowden et al (eds.), Polymers for High Technology Electronics and Photonics, American Chemical Society, Washington, DC, 1987, at 466-483. A number of interconnect technologies have been developed based on copper conductors and polyimide dielectric, offering several advantages over other packaging technologies in meeting the various design needs for high-density, high-speed IC applications. Jensen also provides a partial review of chip attachment techniques. One of these techniques is tape automated bonding (TAB).
TAB technology was introduced a few decades ago as a chip attachment method for high volume applications. It was re introduced a few years ago to meet requirements for high lead-count and high-density LSI and VLSI packages. High capital cost has, however, limited the introduction of TAB technology into such assembly processes. Among the acknowledged problems are that fabrication involves many steps and is costly, and some fabrication technologies do not provide good thermal transfer characteristics. TAB technology has been developed, however, for consumer products produced in very large quantities, such as desktop calculators, watches, cameras, electronic thermometers, and thermal head drivers for facsimile machines. An excellent review of the state of TAB technology is contained, for example, in K. Uehara, "Focusing on Trends in TAB Technology," AEU No. 1, 1988, at 39-44.
Generally speaking, the prior art includes three categories of processes for fabricating multilayer interconnects for applications of the types discussed above. The three types of processes may be referred to as subtractive processes, semi additive processes and additive processes.
Subtractive processes may be understood from the following general description. First, a layer of metal is deposited on a substrate such as a silicon wafer. (The substrate may be an insulating material such as oxidized silicon, or it may be a conductor, in which case there may be an insulating coating on the back.) The metal layer is then patterned into wires, traces, and pad areas using conventional (lithographic) techniques. A dielectric layer is next deposited, following which vias are formed by removing the dielectric over the pads in the first metal layer and then depositing the second layer of metal, by sputtering or other methods. These vias, it should be noted, have side walls which are sloped away from the vertical by a substantial angle (e.g., thirty degrees). Next, the metal layer is patterned using subtractive techniques to remove the metal from unwanted locations leaving the second metal level circuitry and vias. The metal layer may be used as the foundation for another level of interconnect, with the process of building layers being repeated any number of times. Some of the disadvantages of this type of structure are: (1) the sloping sides of the vias cause more area to be allocated to vias than is necessary for their functioning; ( 2) vias cannot be stacked vertically and may have to be laterally offset, requiring more area and reducing heat transfer through the vias; (3) lateral via offset extends the conductive path; and (4) the design rules become quite complex.
Semi-additive processing begins with the deposition of a continuous layer of metal on a substrate. A temporary mask of a dielectric, photoresist, or other suitable material, is applied to the metal. The mask next is patterned and openings are formed where vias are desired. Using the metal layer as a cathode, vias are then electroplated into the openings. The plating mask is then removed. At this juncture, the bottom metal layer is patterned and a dielectric overcoat is applied. Of course, the structure is not yet usable since the vias have not been connected to a next layer of conductors. A variety of approaches have been used for completing the processing. One approach is to mechanically polish off the dielectric overcoat to expose the tops of the vias and to planarize the surface, as described in S. Poon, J. T. Pan, T-C. Wang and B. Nelson, "High Density Multilevel Copper-Polyimide Interconnects," Proceedings of NEPCON West '89, March 1989, at 426-448. A second metal layer can then be deposited and the process can be repeated to build a desired conductor pattern on the second layer, with connection through the first level vias to the bottom conductor layer and with connection through a second level of vias to a third level of conductor. The technique obviously can be extended to produce additional levels.
Semi additive processing thus produces vias with nearly straight side walls allowing, in principle, higher interconnect density than for subtractive processing. It also allows the building of stacked up vias, resulting in shorter conductive paths and, possibly, thermal vias for heat dissipation. Further, the uniformity of the electroplating is easy to control. However, semi-additive processing involves many steps and requires a planarization/process to expose vias and is therefore slow and costly.
The so-called additive processes do not require a temporary plating mask to form vias, as described, for example, in A. C. Adams et al, "High Density Interconnect for Advanced VLSI Packaging," Electrochemical Society Abstracts, Vol. 171, Spring 1987. Vias are plated by electroless techniques in the dielectric. For example, vias are formed in the masked openings by chemical deposition or growth techniques based on use of, for example, nickel as the material for the vias. These vias are solid and have sidewalls that are quite straight and vertical. Though having all the advantages of the semi-additive process, and fewer processing steps, the via uniformity in the electroless process is difficult to control and limits acceptance of these techniques.
These various prior art techniques all have been useful for interconnect manufacturing, but for TAB tape they have thus far been able to yield in production minimum finger spacing of no less than about 50 .mu. and finger widths of no less than about 50 .mu.. These specifications limit the interconnection density of chips and will not be suitable for future generations of chips having one thousand I/O's or more.
Accordingly, it is an object of the present invention to provide an improved multi-layer interconnect structure and method of fabricating same.
It is another object of the invention to provide an improved method for fabricating a flex circuit.
Another object of the invention is to provide a method for making a multi-layer interconnect structure in a TAB tape.
Still another object of the invention is to provide a method for making a multi-layer interconnect structure using smaller inter-conductor line spacings and smaller conductor dimensions than has previously been available for TAB.
Yet another object of the invention is to provide a multi-layer interconnect structure adapted to area bonding techniques.
Another object of the invention is to provide a multi-layer interconnect structure and method of making same, wherein the structure can include a mixture of conductor geometries.
A still further object of the invention is to provide a multi-layer interconnect structure, and method for making same, wherein efficient thermal transfer through the layers can be effected by thermal vias.